The present invention relates generally to the programming of programmable logic devices and more particularly to the programming of programmable logic devices using an interface that operates in either a parallel or a serial control.
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined boolean logic functions. Such a device typically consists of a group of programmable AND gates responsive to a plurality of inputs used to generate a number of predetermined product terms. A typical PLD also comprises a group of fixed/programmable OR gates responsive to the product terms for generating a plurality of sum-of-product (SOP) terms and a macrocell responsive to the sum-of-product terms for generating a desired output.
Typically when designing a programmable logic device, a design engineer must choose between either a parallel programming architecture or a serial programming architecture.
FIG. 1 illustrates a typical prior art parallel programming architecture for a PLD. The parallel architecture 10 generally comprises a set of input buffers 12, a program control detect block 14, a set of address inputs 16, a set of data inputs 18, a set of mode instruction inputs 20, a program control block 22 and an array of programmable elements 24. The address inputs 16, the data inputs 18 and the mode instruction inputs 20 can be registers or merely pins. The input buffers 12 receive a group of parallel inputs at an input 26. The input buffers 12 have a bus 15 that is connected to the address inputs 16, a bus 17 that is connected to the data inputs 18, a bus 19 that is connected to the mode instruction inputs 20 and a bus 21 that is connected to the program control block 22. The program control detect block 14 receives a set of control signals at an input 28. The program control detect block 14 presents signals to the program control block 22 through a bus 23. The address inputs 16, the data inputs 18, the mode instruction inputs 20 and the program control block 22 each have a bus 25, 27, 29 and 31 that is coupled to the array 24. The bus 27 connecting the data inputs 18 and the array 24 is typically a bidirectional bus.
Referring to FIG. 2 a typical prior art serial architecture 30 is shown. The serial architecture 30 is illustrated using primed reference numbers where similar blocks can be compared to the parallel architecture 10 illustrated in FIG. 1. The input buffers 12xe2x80x2 receive a serial input at an input 32 and present the serial input to the address inputs 16xe2x80x2. The address inputs 16xe2x80x2, the data inputs 18xe2x80x2, the mode instruction inputs 20xe2x80x2 and the program control block 22xe2x80x2 are all cascaded together serially through data lines 34, 36 and 38. The program control detect block 14 is replaced by a control select block 40 that receives a control signal at an input 42. The address inputs 16xe2x80x2, the data inputs 18xe2x80x2, the mode instruction inputs 20xe2x80x2 and the program control block 22xe2x80x2 each have a bus that is coupled to the array 24xe2x80x2. It should be appreciated that the parallel architecture 10 illustrated in FIG. 1 does not have the cascaded data lines 34, 36 and 38 as required in the serial architecture 30.
It is therefore an object of the present invention to provide a circuit for providing both serial and parallel programming of a PLD (or CPLD). The present invention reduces the overall number of circuits required to be manufactured by providing a single universal circuit for either serial or parallel programming at the option of the user/programmer.
The present invention provides an integrated parallel and serial programming interface that can be selected by a user/programmer between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.